2 Bit Full Adder :
Verilog Schematic
Verilog Simulation
Cell Layout
Full Chip Layout
DRC Result
LVS Result
Full Chip SPICE Simulation
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Final Project : Delay-Locked Loop
Outline
Over All System
Phase Detector Circuit
Charge Pump
Voltage Control Delay Line
Cell Layout
Full Chip Layout
Verilog Schematic
Verilog Simulation
Cell Layout
Full Chip Layout
DRC Result
LVS Result
Full Chip SPICE Simulation
Outline
Over All System
Phase Detector Circuit
Charge Pump
Voltage Control Delay Line
Cell Layout
Full Chip Layout