// Verilog stimulus file.
// Please do not create a module in this file.
// Default verilog stimulus.
initial
begin

a0 = 1'b0;
a1 = 1'b0;
b0 = 1'b0;
b1 = 1'b0;
c0 = 1'b0;
#400 $finish;
#1 $stop;
end
always #10 a0=~a0;
always #20 b0=~b0;
always #40 a1=~a1;
always #80 b1=~b1;
always #160 c0=~c0;
　
　
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